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CY7C1321BV18 Datasheet 1.8v Synchronous Pipelined Sram

Manufacturer: Cypress (now Infineon)

Overview: CY7C1317BV18 CY7C1917BV18 CY7C1319BV18 CY7C1321BV18 18-Mbit DDR-II SRAM 4-Word Burst.

This datasheet includes multiple variants, all published together in a single manufacturer document.

General Description

• 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) • 300-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600MHz) @ 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Synchronous internally self-timed writes • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–VDD) • Available in 165-ball FBGA package (13 x 15 x 1.4 mm) • Offered in both lead-free and non-lead free packages • JTAG 1149.1 patible test access port • Delay Lock Loop (DLL) for accurate data

Key Features

  • Functional.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture
CY7C132 2K x 8 Dual-Port Static RAM
CY7C1320AV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320CV18 (CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320JV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1323BV25 18-Mbit 4-Word Burst SRAM
CY7C1325 256K x 18 Synchronous 3.3V Cache RAM
CY7C1325G 4-Mbit (256K 횞 18) Flow-Through Sync SRAM

CY7C1321BV18 Distributor