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CY7C1338G - 4-Mbit Flow-Through Sync SRAM

General Description

The CY7C1338G is a 128K × 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic.

Maximum access delay from clock rise is 8.0 ns (100-MHz version).

Key Features

  • 128K × 32 common I/O.
  • 3.3 V core power supply (VDD).
  • 2.5 V or 3.3 V I/O supply (VDDQ).
  • Fast clock-to-output times.
  • 8.0 ns (100-MHz version).
  • Provide high-performance 2-1-1-1 access rate.
  • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences.
  • Separate processor and controller address strobes.
  • Synchronous self-timed write.
  • Asynchronous output enable.
  • Offered in Pb-free 100-pin TQFP package.
  • “ZZ” s.

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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1338 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM
CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM
CY7C1338F 4-Mb (128K x 32) Flow-Through Sync SRAM
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CY7C1339G 4-Mbit Pipelined Sync SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1338G 4-Mbit (128K × 32) Flow-Through Sync SRAM 4-Mbit (128K × 32) Flow-Through Sync SRAM Features ■ 128K × 32 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O supply (VDDQ) ■ Fast clock-to-output times ❐ 8.0 ns (100-MHz version) ■ Provide high-performance 2-1-1-1 access rate ■ User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed write ■ Asynchronous output enable ■ Offered in Pb-free 100-pin TQFP package ■ “ZZ” sleep mode option Functional Description The CY7C1338G is a 128K × 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.0 ns (100-MHz version).