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CY7C1357A - (CY7C1355A / CY7C1357A) 256K x 36/512K x 18 Synchronous Flow-Thru SRAM

This page provides the datasheet information for the CY7C1357A, a member of the CY7C1355A (CY7C1355A / CY7C1357A) 256K x 36/512K x 18 Synchronous Flow-Thru SRAM family.

Description

The CY7C1355A and CY7C1357A SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa.

These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL).

Features

  • Zero Bus Latency, no dead cycles between write and read cycles.
  • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns.
  • Fast clock speed: 133, 117, and 100 MHz.
  • Fast OE access time: 6.5, 7.0, and 7.5ns.
  • Internally synchronized registered outputs eliminate the need to control OE.
  • 3.3V.
  • 5% and +5% power supply 3.3V or 2.5V I/O supply Single WEN (.

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Datasheet preview – CY7C1357A

Datasheet Details

Part number CY7C1357A
Manufacturer Cypress
File Size 776.64 KB
Description (CY7C1355A / CY7C1357A) 256K x 36/512K x 18 Synchronous Flow-Thru SRAM
Datasheet download datasheet CY7C1357A Datasheet
Additional preview pages of the CY7C1357A datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com CY7C1357A CY7C1355A 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL™ Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns • Fast clock speed: 133, 117, and 100 MHz • Fast OE access time: 6.5, 7.0, and 7.5ns • Internally synchronized registered outputs eliminate the need to control OE • • • • • • • • • • • 3.3V –5% and +5% power supply 3.3V or 2.
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