CY7C1366C Datasheet | Cypress

CY7C1366C CY7C1367C 9-Mbit (256K × 36/512K × 18) Pipelined DCD Sync SRAM 9-Mbit (256K × 36/512K × 18) Pipelined DCD Sync SRAM Features - Supports bus operation up to 166 MHz - Available speed grade is 166 MHz - Registered inputs and outputs for pipelined operation - Optimal for performance (double-cycle deselect) - Depth expansion without wait state - 3.3 V - 5% and + 10% core power supply (VDD) - 2.5 V/3.3 V I/O power supply (VDDQ) - Fast clock-to-output times - 3.5 ns (for 166 MHz device) - Provide high performance 3-1-1-1 access rate - User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences - Separate processor and controller address strobes - Synchronous self-timed writes - Asynchronous output enable - Available in Pb-free 100-pin TQFP and non Pb-free 119-ball BGA package - IEEE 1149.1 JTAG-patible boundary scan - “ZZ” sleep mode option Functional Description The CY7C1366C/CY7C1367C SRAM...