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CY7C1372DV25 - 18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Download the CY7C1372DV25 datasheet PDF. This datasheet also covers the CY7C1370DV25 variant, as both devices belong to the same 18-mbit (512k x 36/1m x 18) pipelined sram family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Pin-compatible and functionally equivalent to ZBT™.
  • Supports 200-MHz bus operations with zero wait states.
  • Available speed grades are 200 and 167 MHz.
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE.
  • Fully registered (inputs and outputs) for pipelined operation.
  • Byte write capability.
  • Single 2.5 V core power supply (VDD).
  • 2.5 V I/O power supply (VDDQ).
  • Fast clock-to-output times.
  • 3.0 ns (for 200-MHz devic.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1370DV25-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1372D 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM Cypress
CY7C1372C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress
CY7C1372CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress
CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress
CY7C1370CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1372B (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM
CY7C1372KV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1372KV33 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1372KVE33 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1370B (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C1370DV25 CY7C1372DV25 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture Features ■ Pin-compatible and functionally equivalent to ZBT™ ■ Supports 200-MHz bus operations with zero wait states ❐ Available speed grades are 200 and 167 MHz ■ Internally self-timed output buffer control to eliminate the need to use asynchronous OE ■ Fully registered (inputs and outputs) for pipelined operation ■ Byte write capability ■ Single 2.5 V core power supply (VDD) ■ 2.5 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 3.