CY7C1370B Datasheet (cy7c1370b / Cy7c1372b) 512k X 36/1m X 18 Pipelined Sram

Manufacturer: Cypress (now Infineon)

Overview: CY7C1370B CY7C1372B 512K × 36/1M × 18 Pipelined SRAM with NoBL.

Datasheet Details

Part number	CY7C1370B
Manufacturer	Cypress (now Infineon)
File Size	811.36 KB
Description	(CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM
Datasheet	CY7C1370B_CypressSemiconductor.pdf

Key Features

Zero Bus Latency, no dead cycles between Write and Read cycles.
Fast clock speed: 200, 167, 150, and 133 MHz.
Fast access time: 3.0, 3.4, 3.8, and 4.2 ns.
Internally synchronized registered outputs eliminate the need to control OE.
Single 3.3V.
5% and +10% power supply VDD.
Separate VDDQ for 3.3V or 2.5V I/O.
Single WE (Read/Write) control pin.
Positive clock-edge triggered address, data, and control signal register.

CY7C1370B Distributor & Price

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Similar Datasheet

Part Number	Description	Manufacturer
CY7C1370C	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture	Cypress
CY7C1370CV25	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture	Cypress
CY7C1370D	18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM	Cypress

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