Datasheet4U Logo Datasheet4U.com

CY7C1370B - (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM

General Description

The CY7C1370B and CY7C1372B SRAMs are designed to eliminate dead cycles when transitions from Read to Write or vice versa.

These SRAMs are optimized for 100 percent bus utilization and achieve Zero Bus Latency.

Key Features

  • Zero Bus Latency, no dead cycles between Write and Read cycles.
  • Fast clock speed: 200, 167, 150, and 133 MHz.
  • Fast access time: 3.0, 3.4, 3.8, and 4.2 ns.
  • Internally synchronized registered outputs eliminate the need to control OE.
  • Single 3.3V.
  • 5% and +10% power supply VDD.
  • Separate VDDQ for 3.3V or 2.5V I/O.
  • Single WE (Read/Write) control pin.
  • Positive clock-edge triggered address, data, and control signal register.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress
CY7C1370CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress
CY7C1370D 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM Cypress
CY7C1371C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture Cypress
CY7C1371S 18-Mbit (512K x 36) Flow-Through SRAM Cypress

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1370DV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1370KV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1370KV33 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1370KVE33 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1371B (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C1370B CY7C1372B 512K × 36/1M × 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, and 4.2 ns • Internally synchronized registered outputs eliminate the need to control OE • Single 3.3V –5% and +10% power supply VDD • Separate VDDQ for 3.3V or 2.