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CY7C1373B - (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM

Download the CY7C1373B datasheet PDF. This datasheet also covers the CY7C1371B variant, as both devices belong to the same (cy7c1371b / cy7c1373b) 512k x 36/1m x 18 flow-thru sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The CY7C1371B/CY7C1373B is 3.3V, 512K × 36 and 1M × 18 synchronous flow-thru burst SRAMs, respectively designed to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

Key Features

  • Pin compatible and functionally equivalent to ZBT devices.
  • Supports 117-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE.
  • Registered inputs for flow-thru operation.
  • Byte Write capability.
  • Common I/O architecture.
  • Fast clock-to-output times.
  • 7.5 ns (for 117-MHz device).
  • 8.5 ns (for 100-MHz.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1371B_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1373C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture Cypress
CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress
CY7C1370CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress
CY7C1370D 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM Cypress
CY7C1371C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture Cypress

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1373D 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM
CY7C1373DV25 (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM
CY7C1373KV33 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1370B (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM
CY7C1370DV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
73B CY7C1371B CY7C1373B 512K x 36/1M x 18 Flow-Thru SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT devices • Supports 117-MHz bus operations with zero wait states — Data is transferred on every clock • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Registered inputs for flow-thru operation • Byte Write capability • Common I/O architecture • Fast clock-to-output times — 7.5 ns (for 117-MHz device) — 8.5 ns (for 100-MHz device) • • • • • • • • — 10.0ns (for 83-MHz device) Single 3.3V –5% and +10% power supply VDD Separate VDDQ for 3.3V or 2.