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CY7C1382BV25 - 512K x 36 / 1 Mb x 18 Pipelined SRAM

General Description

The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology.

Each memory cell consists of six transistors.

Key Features

  • Fast clock speed: 200,166, 150, 133 MHz.
  • Provide high-performance 3-1-1-1 access rate.
  • Fast OE access times: 3.0,3.2, 3.4, 3.8, 4.2 ns.
  • Optimal for depth expansion.
  • 2.5V (±5%) Operation.
  • Common data inputs and data outputs.
  • Byte Write Enable and Global Write control.
  • Chip enable for address pipeline.
  • Address, data, and control registers.
  • Internally self-timed WRITE CYCLE.
  • Burst control pins (inter.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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1CY7C1 380B V25 PRELIMINARY CY7C1380BV25 CY7C1382BV25 512K x 36 / 1 Mb x 18 Pipelined SRAM Features • Fast clock speed: 200,166, 150, 133 MHz • Provide high-performance 3-1-1-1 access rate • Fast OE access times: 3.0,3.2, 3.4, 3.8, 4.2 ns • Optimal for depth expansion • 2.