CY7C1424JV18 Description
The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations.
CY7C1424JV18 Key Features
- SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
- 4M x 8 CY7C1429JV18
- 4M x 9 CY7C1423JV18
- 2M x 18 CY7C1424JV18
- 1M x 36