Datasheet4U Logo Datasheet4U.com

CY7C1424JV18 - 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

Download the CY7C1424JV18 datasheet PDF (CY7C1422JV18 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 36-mbit ddr-ii sio sram 2-word burst architecture.

Description

The CY7C1422JV18, CY7C1429JV18, CY7C1423JV18, and CY7C1424JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate I/O (DDR-II SIO) architecture.

The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array.

Features

  • Functional.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1422JV18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

  • CY7C1460SV25 - 36-Mbit (1M x 36/2M x 18) Pipelined SRAM (Cypress)
  • CY7C1462SV25 - 36-Mbit (1M x 36/2M x 18) Pipelined SRAM (Cypress)
  • CY7C1006D - 1-Mbit (256K x 4) Static RAM (Cypress)
  • CY7C1011G - 2-Mbit (128K words x 16 bit) Static RAM (Cypress)
  • CY7C1041G - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1041GE - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1041GN - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1049GN - 4-Mbit (512K words x 8 bit) Static RAM (Cypress)
  • CY7C1061DV33 - 16-Mbit (1 M X 16) Static RAM (Cypress)
  • CY7C1061G - 16-Mbit (1 M words x 16 bit) Static RAM (Cypress)
Other Datasheets by Cypress Semiconductor
  • CY7C1424AV18 - 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
  • CY7C1424BV18 - 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
  • CY7C1424KV18 - 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture
  • CY7C142 - 2K x 8 Dual-Port Static RAM
  • CY7C1420AV18 - (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture
  • CY7C1420BV18 - 36-Mbit DDR-II SRAM 2-Word Burst Architecture
  • CY7C1420JV18 - 36-Mbit DDR-II SRAM 2-Word Burst Architecture
  • CY7C1420KV18 - 36-Mbit DDR II SRAM Two-Word Burst Architecture

Full PDF Text Transcription

Click to expand full text
CY7C1422JV18, CY7C1429JV18 CY7C1423JV18, CY7C1424JV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ Functional Description The CY7C1422JV18, CY7C1429JV18, CY7C1423JV18, and CY7C1424JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate I/O (DDR-II SIO) architecture. The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus.
Published: |