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CY7C1424KV18 Datasheet 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1423KV18/CY7C1424KV18 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture 36-Mbit DDR II SIO SRAM Two-Word Burst.

Download the CY7C1424KV18 datasheet PDF. This datasheet also includes the CY7C1423KV18 variant, as both parts are published together in a single manufacturer document.

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Key Features

  • 36-Mbit density (2M × 18, 1M × 36).
  • 333 MHz clock for high bandwidth.
  • Two-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo clocks (CQ and CQ) simplify data capture in high speed systems.
  • Synchronous in.

CY7C1424KV18 Distributor & Price

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