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CY7C1427AV18 Datasheet

(cy7c14xxav18) 36-mbit Ddr-ii Sram 2-word Burst Architecture

Manufacturer: Cypress (now Infineon)

This datasheet includes multiple variants, all published together in a single manufacturer document.

CY7C1427AV18 Overview

The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K.

CY7C1427AV18 Key Features

  • 250-MHz clock for high bandwidth
  • 2-Word burst for reducing address bus frequency
  • Double Data Rate (DDR) interfaces (data transferred at 500 MHz) @ 250 MHz
  • Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
  • Two output clocks (C and C) account for clock skew and flight time mismatching
  • Echo clocks (CQ and CQ) simplify data capture in high-speed systems
  • Synchronous internally self-timed writes
  • 1.8V core power supply with HSTL inputs and outputs
  • Variable drive HSTL output buffers

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1427BV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1427JV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C142 2K x 8 Dual-Port Static RAM
CY7C1420AV18 (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1420BV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1420JV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1420KV18 36-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1421AV18 1.8V Synchronous Pipelined SRAM
CY7C1422AV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1422BV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

CY7C1427AV18 Distributor