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CY7C1441KV33 - 36-Mbit (1M x 36/2M x 18) Flow-Through SRAM

General Description

The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 are 3.3 V, 1M × 36/2M ×

Key Features

  • Supports 133-MHz bus operations.
  • 1M × 36/2M × 18 common I/O.
  • 3.3 V core power supply.
  • 2.5 V or 3.3 V I/O power supply.
  • Fast clock-to-output times.
  • 6.5 ns (133 MHz version).
  • Provide high-performance 2-1-1-1 access rate.
  • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences.
  • Separate processor and controller address strobes.
  • Synchronous self-timed write.
  • Asynchronous output enable.
  • CY7C1441KV33, C.

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CY7C1441KVE33 36-Mbit (1M x 36/2M x 18) Flow-Through SRAM
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1441KV33 CY7C1443KV33 CY7C1441KVE33 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM (With ECC) 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM (With ECC) Features ■ Supports 133-MHz bus operations ■ 1M × 36/2M × 18 common I/O ■ 3.3 V core power supply ■ 2.5 V or 3.3 V I/O power supply ■ Fast clock-to-output times ❐ 6.5 ns (133 MHz version) ■ Provide high-performance 2-1-1-1 access rate ■ User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed write ■ Asynchronous output enable ■ CY7C1441KV33, CY7C1443KV33, and CY7C1441KVE33 are available in JEDEC-standard 100-pin TQFP and 165-ball FBGA Pb-free packages. ■ IEEE 1149.