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CY7C1445KV33 - 36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM

Download the CY7C1445KV33 datasheet PDF. This datasheet also covers the CY7C1444KV33 variant, as both devices belong to the same 36-mbit (1m x 36/2m x 18) pipelined dcd sync sram family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1444KV33/CY7C1445KV33 SRAMs integrate 1M × 36/2M × 18 SRAM cells with advanced sy

Features

  • Supports bus operation up to 250 MHz.
  • Available speed grades is 250 MHz.
  • Registered inputs and outputs for pipelined operation.
  • Optimal for performance (double-cycle deselect).
  • Depth expansion without wait state.
  • 3.3-V core power supply.
  • 2.5-V or 3.3-V I/O power supply.
  • Fast clock-to-output times.
  • 2.5 ns (for 250-MHz device).
  • Provide high-performance 3-1-1-1 access rate.
  • User-selectable burst counter supporting interleaved or line.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1444KV33-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1460SV25 36-Mbit (1M x 36/2M x 18) Pipelined SRAM Cypress
CY7C1462SV25 36-Mbit (1M x 36/2M x 18) Pipelined SRAM Cypress
CY7C1006D 1-Mbit (256K x 4) Static RAM Cypress
CY7C1011G 2-Mbit (128K words x 16 bit) Static RAM Cypress
CY7C1041G 4-Mbit (256K words x 16 bit) Static RAM Cypress

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C144 8K x 9/0 Dual-Port Static RAM
CY7C1440AV25 36-Mbit Pipelined Sync SRAM
CY7C1440AV33 (CY7C144xAV33) Sync SRAM
CY7C1440KV25 36-Mbit (1M x 36) Pipelined Sync SRAM
CY7C1440KV33 36-Mbit Pipelined Sync SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C1444KV33 CY7C1445KV33 36-Mbit (1M × 36/2M × 18) Pipelined DCD Sync SRAM 36-Mbit (1M × 36/2M × 18) Pipelined DCD Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades is 250 MHz ■ Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ■ Depth expansion without wait state ■ 3.3-V core power supply ■ 2.5-V or 3.3-V I/O power supply ■ Fast clock-to-output times ❐ 2.
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