CY7C1461AV33 - Flow-Through SRAM

Description

The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33[1] are 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-Through Burst SRAMs designed specifically to support unlimited true back-to-back read and write operations without the insertion of wait states.

Features

Functional.

Cypress Semiconductor

📥 Download Datasheet

Datasheet Details

Part number	CY7C1461AV33
Manufacturer	Cypress
File Size	884.01 KB
Description	Flow-Through SRAM
Datasheet	CY7C1461AV33 Datasheet
Additional preview pages of the CY7C1461AV33 datasheet.

📁 Similar Datasheet

CY7C1460SV25 - 36-Mbit (1M x 36/2M x 18) Pipelined SRAM (Cypress)
CY7C1462SV25 - 36-Mbit (1M x 36/2M x 18) Pipelined SRAM (Cypress)
CY7C1006D - 1-Mbit (256K x 4) Static RAM (Cypress)
CY7C1011G - 2-Mbit (128K words x 16 bit) Static RAM (Cypress)
CY7C1041G - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
CY7C1041GE - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
CY7C1041GN - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
CY7C1049GN - 4-Mbit (512K words x 8 bit) Static RAM (Cypress)
CY7C1061DV33 - 16-Mbit (1 M X 16) Static RAM (Cypress)
CY7C1061G - 16-Mbit (1 M words x 16 bit) Static RAM (Cypress)

Other Datasheets by Cypress Semiconductor

CY7C1461AV25 - Flow-Through SRAM
CY7C1461KV33 - 36-Mbit (1M x 36/2M x 18) Flow-Through SRAM
CY7C146 - 2K x 8 Dual-Port Static RAM
CY7C1460AV25 - 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM
CY7C1460AV33 - 36-Mbit Pipelined SRAM
CY7C1460BV25 - 36-Mbit (1 M x 36/2 M x 18) Pipelined SRAM
CY7C1460KV25 - 36-Mbit (1M x 36/2M x 18) Pipelined SRAM
CY7C1460KV33 - 36-Mbit (1M x 36/2M x 18) Pipelined SRAM

Full PDF Text Transcription

Click to expand full text

CY7C1461AV33 www.DataSheet4U.com CY7C1463AV33, CY7C1465AV33 36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture Features ■ ■ Functional Description The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33[1] are 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-Through Burst SRAMs designed specifically to support unlimited true back-to-back read and write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is equipped with the advanced NoBL logic required to enable consecutive read and write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

Published: Mar 13, 2010 |