CY7C1482BV33 Datasheet | Cypress

CY7C1480BV33 CY7C1482BV33, CY7C1486BV33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features - - - - - - Functional Description The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at the rising edge of the clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses may be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self timed write cycle.This part supports byte write operations (see sections Pin Definitions on page 7 and Truth Table on page 10 for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC standard JESD8-5 patible. For best practices remendations, refer to the Cypress application note AN1064 “SRAM System Guidelines”. Supports bus operation up to 250 MHz Available speed grades are 250, 200, and 167 MHz Registered inputs and outputs for pipelined operation 3.3V core power supply 2.5V/3.3V IO operation Fast clock-to-output times - 3.0 ns (for 250 MHz device) Provide high performance 3-1-1-1...