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CY7C1484V33 - 2M x 36/4M x 18 Pipelined DCD SRAM

This page provides the datasheet information for the CY7C1484V33, a member of the CY7 2M x 36/4M x 18 Pipelined DCD SRAM family.

Datasheet Summary

Description

The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology.

Each memory cell consists of six transistors.

Features

  • Fast clock speed: 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate Fast access time: 2.6, 3.0, and 3.4 ns Optimal for depth expansion Single 3.3V.
  • 5% and +5% power supply VDD Separate VDDQ for 3.3V or 2.5V Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for add.

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Datasheet preview – CY7C1484V33

Datasheet Details

Part number CY7C1484V33
Manufacturer Cypress Semiconductor
File Size 507.67 KB
Description 2M x 36/4M x 18 Pipelined DCD SRAM
Datasheet download datasheet CY7C1484V33 Datasheet
Additional preview pages of the CY7C1484V33 datasheet.

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Other Datasheets by Cypress Semiconductor
  • CY7C148 - (CY7C148 / CY7C149) 1K x 4 Static RAM
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  • CY7C1480V33 - (CY7C1480V33 / CY7C1482V33 / CY7C1486V33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
  • CY7C1481V25 - 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
  • CY7C1481V33 - (CY7C1481V33 / CY7C1483V33 / CY7C1487V33) 2M x 36/4M x 18/1M x 72 Flow-Through SRAM
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  • CY7C1482BV33 - (CY7C148xBV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

Full PDF Text Transcription

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PRELIMINARY CY7C1484V33 CY7C1485V33 2M x 36/4M x 18 Pipelined DCD SRAM Features • • • • • • • • • • • • • • • • • Fast clock speed: 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate Fast access time: 2.6, 3.0, and 3.4 ns Optimal for depth expansion Single 3.3V –5% and +5% power supply VDD Separate VDDQ for 3.3V or 2.5V Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for address pipeline Address, data, and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications High-density, high-speed packages JTAG boundary scan for BGA packaging version Available in 119-ball bump BGA and 100-pin TQFP packages (CY7C1484V33 and CY7C1485V33).
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