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CY7C1513KV18 - (CY7C15xxKV18) 72-Mbit QDR II SRAM 4-Word Burst Architecture

This page provides the datasheet information for the CY7C1513KV18, a member of the CY7C1511KV18 (CY7C15xxKV18) 72-Mbit QDR II SRAM 4-Word Burst Architecture family.

Datasheet Summary

Description

The CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II architecture.

QDR II architecture consists of two separate ports: the read port and the write port to access the memory array.

Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 333 MHz clock for high bandwidth.
  • Four-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo cl.

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Datasheet preview – CY7C1513KV18

Datasheet Details

Part number CY7C1513KV18
Manufacturer Cypress Semiconductor
File Size 843.99 KB
Description (CY7C15xxKV18) 72-Mbit QDR II SRAM 4-Word Burst Architecture
Datasheet download datasheet CY7C1513KV18 Datasheet
Additional preview pages of the CY7C1513KV18 datasheet.

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Full PDF Text Transcription

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CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 72-Mbit QDR® II SRAM Four-Word Burst Architecture 72-Mbit QDR® II SRAM Four-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 333 MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Single multiplexed address input bus latches address inputs for read and write ports ■ Separate port selects for depth expan
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