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CY7C1515AV18 - 72-Mbit QDR-II SRAM 4-Word Burst Architecture

This page provides the datasheet information for the CY7C1515AV18, a member of the CY7C1511AV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture family.

Datasheet Summary

Description

The CY7C1511AV18, CY7C1526AV18, CY7C1513AV18, and CY7C1515AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.

QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array.

Features

  • Configurations CY7C1511AV18.
  • 8M x 8 CY7C1526AV18.
  • 8M x 9 CY7C1513AV18.
  • 4M x 18 CY7C1515AV18.
  • 2M x 36 Separate independent read and write data ports.
  • Supports concurrent transactions 300 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.

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Datasheet preview – CY7C1515AV18

Datasheet Details

Part number CY7C1515AV18
Manufacturer Cypress Semiconductor
File Size 756.21 KB
Description 72-Mbit QDR-II SRAM 4-Word Burst Architecture
Datasheet download datasheet CY7C1515AV18 Datasheet
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