CY7C1522AV18 - 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

Cypress (now Infineon)

General Description

The CY7C1522AV18, CY7C1529AV18, CY7C1523AV18, and CY7C1524AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO (DDR-II SIO) architecture.

The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array.

Key Features

Functional.

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CY7C1522AV18 72-mbit ddr-ii sio sram 2-word burst architecture by Cypress (now Infineon) - Datasheet Preview

Datasheet Details

Part number	CY7C1522AV18
Manufacturer	Cypress (now Infineon)
File Size	735.55 KB
Description	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
Datasheet	CY7C1522AV18 Datasheet

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Other Datasheets by Cypress (now Infineon)

Part Number	Description
CY7C1522JV18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522KV18	72-Mbit DDR II SIO SRAM 2-Word Burst Architecture
CY7C1522V18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1520KV18	72-Mbit DDR-II SRAM Two-Word Burst Architecture
CY7C1520V18	1.8V Synchronous Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1522AV18, CY7C1529AV18 CY7C1523AV18, CY7C1524AV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ Functional Description The CY7C1522AV18, CY7C1529AV18, CY7C1523AV18, and CY7C1524AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO (DDR-II SIO) architecture. The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is accomplished through a common address bus.