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CY7C1522V18 Datasheet 72-mbit Ddr-ii Sio Sram 2-word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1522V18 CY7C1529V18 CY7C1523V18 CY7C1524V18 72-Mbit DDR-II SIO SRAM 2-Word Burst.

General Description

The CY7C1522V18, CY7C1529V18, CY7C1523V18, CY7C1524V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II SIO (Double Data Rate Separate I/O) architecture.

The DDR-II SIO consists of two separate ports to access the memory array.

The Read port has dedicated Data outputs and the Write port has dedicated Data inputs to pletely eliminate the need to “turn around’ the data bus required with mon I/O devices.

Key Features

  • 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36).
  • 300-MHz clock for high bandwidth.
  • 2-Word burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.
  • Echo clocks (CQ and CQ) simplify data captu.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1522AV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522JV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522KV18 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture
CY7C1520KV18 72-Mbit DDR-II SRAM Two-Word Burst Architecture
CY7C1520V18 1.8V Synchronous Pipelined SRAM
CY7C1521KV18 72-Mbit DDR II SRAM Four-Word Burst Architecture
CY7C1521V18 1.8V Synchronous Pipelined SRAM
CY7C1523AV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1523JV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1523KV18 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture

CY7C1522V18 Distributor