CY7C1526KV18 Description
QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.
CY7C1526KV18 Key Features
- Separate independent read and write data ports
- Supports concurrent transactions
- 333 MHz clock for high bandwidth
- Four-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces on both read and write ports
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock
- Echo clocks (CQ and CQ) simplify data capture in high speed
- Single multiplexed address input bus latches address inputs