CY7C1529V18 Datasheet | Cypress

CY7C1522V18 CY7C1529V18 CY7C1523V18 CY7C1524V18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features - 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36) - 300-MHz clock for high bandwidth - 2-Word burst for reducing address bus frequency - Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz - Two input clocks (K and K) for precise DDR timing - SRAM uses rising edges only - Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches - Echo clocks (CQ and CQ) simplify data capture in high-speed systems - Synchronous internally self-timed writes - 1.8V core power supply with HSTL inputs and outputs - Variable drive HSTL output buffers - Expanded HSTL output voltage (1.4V- VDD) - Available in 165-ball FBGA package (15 x 17 x 1.4 mm ) - Offered in lead-free and non lead-free packages - JTAG 1149.1 patible test access port - Delay Lock Loop (DLL) for accurate data placement Functional Description The CY7C1522V18, CY7C1529V18, CY7C1523V18, CY7C1524V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II SIO (Double Data Rate Separate I/O) architecture. The DDR-II SIO consists of two separate ports to access the memory array. The Read port has dedicated Data outputs and the Write port has dedicated Data inputs to pletely eliminate the need to “turn around’ the data bus required with mon I/O devices. Access to each port is acplished using a mon address bus. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1522V18, two 9-bit words in the case of CY7C1529V18, two 18-bit words in the case of CY7C1523V18, and two 36-bit words in the case of CY7C1524V18, that burst sequentially into or out of the...