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CY7C1545KV18 Datasheet 72-mbit Qdr Ii+ Sram Four-word Burst Architecture

Manufacturer: Cypress (now Infineon)

This datasheet includes multiple variants, all published together in a single manufacturer document.

Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 450 MHz clock for high bandwidth.
  • Four-word burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz.
  • Available in 2.0 clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high speed sys.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1543KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1548KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C150 1Kx4 Static RAM
CY7C1510AV18 72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1510V18 1.8V Synchronous Pipelined SRAM
CY7C1511AV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511JV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511KV18 (CY7C15xxKV18) 72-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1511V18 (CY7C15xxV18) SRAM 4-Word Burst Architecture
CY7C1512 64K x 8 Static RAM

CY7C1545KV18 Distributor