CY7C1612KV18- 144-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1613KV18- 144-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1614KV18- 144-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1615KV18- 144-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1618KV18- 144-Mbit DDR II SRAM Two-Word Burst Architecture
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CY7C1663KV18/CY7C1665KV18
144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
Features
■ Separate independent read and write data ports ❐ Supports concurrent transactions
■ 550-MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces on both read and write ports
(data transferred at 1100 MHz) at 550 MHz ■ Available in 2.
CY7C1663KV18 Datasheet
