CY7C168A Datasheet | Cypress

4Kx4 RAM Features - Automatic power-down when deselected - CMOS for optimum speed/power - High speed - t AA = 15 ns - Low active power - 633 m W - Low standby power - 110 m W - TTL-patible inputs and outputs - VIH of 2.2V - Capable of withstanding greater than 2001V electrostatic discharge Functional Description The CY7C168A is a high-performance CMOS static RAM organized as 4096 by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and three-state drivers. The CY7C168A has an automatic power-down feature, reducing the power consumption by 77% when deselected. Writing to the device is acplished when the Chip Select (CE) and Write Enable (WE) inputs are both LOW. Data on the four data input/output pins (I/O0 through I/O3) is written into the memory location specified on the address pins (A0 through A11). Reading the device is acplished by taking the Chip Enable (CE) LOW, while Write Enable (WE) remains HIGH. Under these conditions, the contents of the location specified on the address pins will appear on the four data input/output pins (I/O0 through I/O3). The input/output pins remain in a high-impedance state when Chip Enable (CE) is HIGH or Write Enable (WE) is LOW. A die coat is used to insure alpha immunity. Logic Block Diagram Pin Configurations DIP/SOJ Top View A4 A5 A6 A7 A8 A9 A10 A11 CE GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 7C168A 16 15 14 13 12 11 INPUTBUFFER A0 A1 A2 A3 A4 A5 A6 ROW DECODER I/O0 SENSE AMP 128 x 128 ARRAY I/O1 I/O2 I/O3 VCC A3 A2 A1 A0 I/O 0 I/O 1 I/O 2 I/O 3 WE C168A-2 COLUMN DECODER POWER DOWN (7C168A) CE...