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CY7C1911KV18 - 18-Mbit QDR II SRAM Four-Word Burst Architecture

Download the CY7C1911KV18 datasheet PDF. This datasheet also covers the CY7C1311KV18 variant, as both devices belong to the same 18-mbit qdr ii sram four-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 333-MHz clock for high bandwidth.
  • Four-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two Input Clocks for Output Data (C and C) to minimize Clock skew and flight time mismatches.
  • Echo cl.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1311KV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1911BV18 (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1911CV18 (CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1911JV18 (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1910BV18 1.8V Synchronous Pipelined SRAM
CY7C1916BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
 CY7C1311KV18/CY7C1911KV18 CY7C1313KV18/CY7C1315KV18 18-Mbit QDR® II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 333-MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two Input Clocks for Output Data (C and C) to minimize Clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Single multiplexed address input bus latches address inputs for read and write ports ■ Separate port selects