CY7C1911KV18 - 18-Mbit QDR II SRAM Four-Word Burst Architecture

This page provides the datasheet information for the CY7C1911KV18, a member of the CY7C1311KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture family.

Product Overview

Cypress Semiconductor

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Datasheet Details

Part number	CY7C1911KV18
Manufacturer	Cypress Semiconductor
File Size	657.31 KB
Description	18-Mbit QDR II SRAM Four-Word Burst Architecture
Datasheet	CY7C1911KV18 Datasheet
Additional preview pages of the CY7C1911KV18 datasheet.

CY7C1911KV18 Product details

Features

Separate independent read and write data ports.
Supports concurrent transactions.
333-MHz clock for high bandwidth.
Four-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two Input Clocks for Output Data (C and C) to minimize Clock skew and flight time mismatches.
Echo cl.

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Published: Mar 14, 2017 |