Datasheet Summary
CY7C1311KV18/CY7C1911KV18 CY7C1313KV18/CY7C1315KV18
18-Mbit QDR® II SRAM Four-Word Burst Architecture
18-Mbit QDR® II SRAM Four-Word Burst Architecture
Features
- Separate independent read and write data ports
- Supports concurrent transactions
- 333-MHz clock for high bandwidth
- Four-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two Input Clocks for Output Data (C and C) to minimize Clock skew and flight time mismatches
- Echo clocks (CQ and CQ) simplify data capture in high speed systems
- Single...