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CY7C1917BV18 Datasheet 1.8V Synchronous Pipelined SRAM

Manufacturer: Cypress (now Infineon)

Download the CY7C1917BV18 datasheet PDF. This datasheet also includes the CY7C1317BV18 variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (CY7C1317BV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

General Description

• 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) • 300-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600MHz) @ 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Synchronous internally self-timed writes • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–VDD) • Available in 165-ball FBGA package (13 x 15 x 1.4 mm) • Offered in both lead-free and non-lead free packages • JTAG 1149.1 compatible test access port • Delay Lock Loop (DLL) for accurate data

Overview

CY7C1317BV18 CY7C1917BV18 CY7C1319BV18 CY7C1321BV18 18-Mbit DDR-II SRAM 4-Word Burst.

Key Features

  • Functional.

More Datasheets from Cypress (now Infineon)

Part Number Description
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