CY7C196 Datasheet | Cypress

Features e h S a at .D w w w Functional Description CY7C194 CY7C195 CY7C196 64K x 4 Static RAM able(s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the CY7C196) and three-state drivers. They have an automatic power-down feature , reducing the power consumption by 75% when deselected. Writing to the device is acplished when the Chip Enable(s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the CY7C196) and Write Enable (WE) inputs are both LOW. Data on the four input pins (I/O0 through I/O3) is written into the memory location, specified on the address pins (A0 through A15). Reading the device is acplished by taking the Chip Enable(s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the CY7C196) LOW, while Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the four data I/O pins. A die coat is used to ensure alpha immunity. - High speed - 12 ns - Output enable (OE) feature (7C195 and 7C196) - CMOS for optimum speed/power - Low active power - 880 m W - Low standby power - 220 m W - TTL-patible inputs and outputs - Automatic power-down when deselected The CY7C194, CY7C195, and CY7C196 are high-performance CMOS static RAMs organized as 65,536 by 4 bits. Easy memory expansion is provided by active LOW Chip En- Logic Block Diagram INPUT BUFFER A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 1024 x 64 x 4 ARRAY m o .c U 4 t e e h S a t a .D w w w Pin Configurations DIP/SOJ Top View 24 23 22 21 20 19 18 17 16 15 14 13 DIP/SOJ Top View 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 ROW DECODER I/O3 I/O2 CE GND 1 2 3 4 5 6 7C194 7 8 9 10 11 12 VCC A5 A4 A3 A2 A1 A0 I/O3 I/O2 I/O1 I/O0 WE SENSE AMPS NC A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE1 OE GND 1 2 3 4 5 6 7C195 7 7C196 8 9 10 11 12 13 14 VCC A5 A4 A3 A2 A1 A0 NC I/O3 I/O2 I/O1 I/O0 WE C194-3 CE2 (7C196) NC (7C195) C194-2 I/O1 I/O0 COLUMN...