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CY7C331 - Asynchronous Registered EPLD

Datasheet Summary

Description

The CY7C331 is the most versatile PLD available for asynchronous designs.

Central resources include twelve full D-type flip-flops with separate set, reset, and clock capability.

Features

  • Twelve I/O macrocells each having:.
  • One state flip-flop with an XOR sum-of-products input.
  • One feedback flip-flop with input coming from the I/O pin.
  • Independent (product term) set, reset, and clock inputs on all registers.
  • Asynchronous bypass capability on all registers under product term control (r = s = 1).
  • Global or local output enable on three-state I/O.
  • Feedback from either registe.

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Datasheet preview – CY7C331

Datasheet Details

Part number CY7C331
Manufacturer Cypress Semiconductor
File Size 361.24 KB
Description Asynchronous Registered EPLD
Datasheet download datasheet CY7C331 Datasheet
Additional preview pages of the CY7C331 datasheet.

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