CY7C331 Description
The CY7C331 is the most versatile PLD available for asynchronous designs. Central resources include twelve full D-type flip-flops with separate set, reset, and clock capability. For increased utility, XOR gates are provided at the D-inputs and the product term allocation per flip-flop is variably distributed.
CY7C331 Key Features
- Twelve I/O macrocells each having
- One state flip-flop with an XOR sum-of-products input
- One feedback flip-flop with input ing from the I/O pin
- Independent (product term) set, reset, and clock inputs on all registers
- Asynchronous bypass capability on all registers under product term control (r = s = 1)
- Global or local output enable on three-state I/O
- Feedback from either register to the array 192 product terms with variable distribution to macrocells 13 inputs, 12 feed
- Low power
- 90 mA typical ICC quiescent
- 180 mA ICC maximum