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CY7C335 - Universal Synchronous EPLD

General Description

The CY7C335 is a high-performance, erasable, programmable logic device (EPLD) whose architecture has been optimized to enable the user to easily and efficiently construct very high performance state machines.

Key Features

  • 100-MHz output registered operation.
  • Twelve I/O macrocells, each having:.
  • Registered, three-state I/O pins.
  • Input and output register clock select multiplexer.
  • Feed back multiplexer.
  • Output enable (OE) multiplexer Bypass on input and output registers All twelve macrocell state registers can be hidden User configurable I/O macrocells to impleme.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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1CY 7C33 5 fax id: 6018 CY7C335 www.DataSheet4U.