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CY7C9335A - SMPTE-259M/DVB-ASI Descrambler/Framer-Controller

Description

SMPTE-259M Operation

The CY7C9335A is a CMOS integrated circuit designed to decode SMPTE-125M bit-parallel digital characters (or other data formats) using the SMPTE-259M decoding rules.

Features

  • Fully compatible with SMPTE-259M.
  • Fully compatible with DVB-ASI.
  • Operates from a single +5V supply.
  • 100-pin TQFP package.
  • Decodes 10-bit parallel digital streams for 27M characters/sec (270 Mbits/sec serial).
  • Operates with CY7B9334 SMPTE HOTLink deserializer/receiver The inputs of the CY7C9335A are designed to be directly mated to a CY7B9334 HOTLink receiver, which converts the SMPTE-259M compatible high-speed serial data stream into 10-bit.

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Datasheet preview – CY7C9335A

Datasheet Details

Part number CY7C9335A
Manufacturer Cypress (now Infineon)
File Size 117.17 KB
Description SMPTE-259M/DVB-ASI Descrambler/Framer-Controller
Datasheet download datasheet CY7C9335A Datasheet
Additional preview pages of the CY7C9335A datasheet.

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Full PDF Text Transcription

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CY7C9335A SMPTE-259M/DVB-ASI Descrambler/Framer-Controller Features • Fully compatible with SMPTE-259M • Fully compatible with DVB-ASI • Operates from a single +5V supply • 100-pin TQFP package • Decodes 10-bit parallel digital streams for 27M characters/sec (270 Mbits/sec serial) • Operates with CY7B9334 SMPTE HOTLink deserializer/receiver The inputs of the CY7C9335A are designed to be directly mated to a CY7B9334 HOTLink receiver, which converts the SMPTE-259M compatible high-speed serial data stream into 10-bit parallel characters. This device performs both TRS (sync) detection and framing, data descrambling with the SMPTE-259M X9+X4+1 algorithm, and NRZI-to-NRZ decoding. These functions operate at a 27 MHz character rate.
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