CY8C3245 Datasheet | Cypress

Description PSo C® 3 is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and a microcontroller on a single chip. The PSo C 3 architecture boosts performance through: - 8051 core plus DMA controller at up to 50 MHz - Ultra low power with industry's widest voltage range - Programmable digital and analog peripherals enable custom functions - Flexible routing of any analog or digital peripheral function to any pin PSo C devices employ a highly configurable system-on-chip architecture for embedded control design. They integrate configurable analog and digital circuits, controlled by an on-chip microcontroller. A single PSo C device can integrate as many as 100 digital and analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality. Features - Operating characteristics  Voltage range: 1.71 to 5.5 V, up to six power domains  Temperature range (ambient) - 40 to 85 °C[1]  DC to 50-MHz operation  Power modes - Active mode 1.2 m A at 6 MHz, and 12 m A at 48 MHz - 1-µA sleep mode - 200-n A hibernate mode with RAM retention  Boost regulator from 0.5-V input up to 5-V output - Performance  8-bit 8051 CPU, 32 interrupt inputs  24-channel direct memory access (DMA) controller - Memories  Up to 64 KB program flash, with cache and security features  Up to 8 KB additional flash for error correcting code (ECC)  Up to 8 KB RAM  Up to 2 KB EEPROM - Digital peripherals  Four 16-bit timer, counter, and PWM (TCPWM) blocks  I2C, 1 Mbps bus speed  USB 2.0 certified Full-Speed (FS) 12 Mbps peripheral interface (TID#40770053) using internal oscillator[2]  16 to 24 universal digital blocks (UDB), programmable to create any number of functions: - 8-, 16-, 24-, and 32-bit timers, counters, and PWMs - I2C, UART, SPI, I2S, LIN 2.0 interfaces - Cyclic redundancy check (CRC) - Pseudo random sequence (PRS) generators - Quadrature decoders - Gate-level logic...