CYDMX128B16 Overview
..................................................... 4 Power Supply .............................................................. 4 ADM Interface Read or Write Operation .....................
CYDMX128B16 Key Features
- True dual-ported memory block that allow simultaneous independent access
- One port with dedicated time multiplexed address and data (ADM) interface
- One port configurable to standard SRAM or time multiplexed address and data interface 16 K/8 K/4 K × 16 memory configura
- 65 ns or 90 ns ADM interface
- 40 ns or 60 ns standard SRAM interface Fully asynchronous operation Port independent 1.8 V, 2.5 V, and 3.0 V IOs
- Active: ICC = 15 mA (typical) at 90 ns
- Active: ICC = 25 mA (typical) at 65 ns
- Standby: ISB3 = 2 A (typical) Port independent power down On-chip arbitration logic Mailbox interrupt for port to port
- Block Diagram
- 198 Champion Court