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CYF0072V - 18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO

Download the CYF0072V datasheet PDF (CYF0018V included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 18/36/72 mbit programmable fifos master reset to clear entire fifo.

Description

The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device.

It has independent read and write ports, which can be clocked up to 133 MHz.

User can configure input and output bus sizes.

Features

  • Functional.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CYF0018V_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number CYF0072V
Manufacturer Cypress (Infineon)
File Size 606.22 KB
Description 18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
Datasheet download datasheet CYF0072V Datasheet

📁 Similar Datasheet

Other Datasheets by Cypress Semiconductor
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Full PDF Text Transcription

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CYF0018V, CYF0036V CYF0072V 18/36/72 Mbit Programmable FIFOs 18/36/72/144 Mbit Programmable FIFOs Features ■ Functional Description The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 133 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 4.8 Gbps. The read and write ports can support multiple I/O voltage standards. The user-programmable registers enable user to configure the device operation as desired. The device also offers a simple and easy-to-use interface to reduce implementation and debugging efforts, improve time-to-market, and reduce engineering costs.
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