CYK001M16ZCCA Datasheet | Cypress

.. CYK001M16ZCCA Mo BL3™ 16-Mbit (1M x 16) Pseudo Static RAM Features - Wide voltage range: 2.70V- 3.30V - Access Time: 55 ns, 70 ns - Ultra-low active power - Typical active current: 3 m A @ f = 1 MHz - Typical active current: 13 m A @ f = fmax - Ultra low standby power - Automatic power-down when deselected - CMOS for optimum speed/power - Deep Sleep Mode - Offered in a 48-ball BGA Package (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). Writing to the device is acplished by asserting Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is acplished by asserting Chip Enable (CE) and Output Enable (OE) inputs LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. Refer to the truth table for a plete description of read and write modes. This device incorporates a Low Power mode wherein data integrity is not guaranteed, but Power Consumption reduces to less than 100 µW. This mode (Deep Sleep Mode) is enabled by driving ZZ LOW.See the Truth Table for a plete description of Read, Write, and Deep Sleep mode. Functional Description The CYK001M16ZCCAU is a high-performance CMOS Pseudo static RAM organized as 1M words by 16 bits that supports an asynchronous memory interface. This device Features advanced circuit design to provide...