CYK128K16MCCB Datasheet | Cypress

2-Mbit (128K x 16) Pseudo Static RAM Features - Wide voltage range: 2.70V- 3.30V - Access Time: 55 ns, 70 ns - Ultra-low active power - Typical active current: 1m A @ f = 1 MHz - Typical active current: 14 m A @ f = fmax (For 55-ns) - Typical active current: 8 m A @ f = fmax (For 70-ns) - Ultra low standby power .. can be put into standby mode when deselected (CE HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the chip is deselected (CE HIGH), or when the outputs are disabled (OE HIGH), or when both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). Writing to the device is acplished by asserting Chip Enable (CE LOW) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is acplished by asserting Chip Enable (CE LOW) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. Refer to the truth table for a plete description of read and write modes. - Automatic power-down when deselected - CMOS for optimum speed/power - Offered in a 48-ball BGA Package Functional Description[1] The CYK128K16MCCB is a high-performance CMOS Pseudo Static RAM organized as 128K words by 16 bits that supports an asynchronous memory interface. This device Features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (Mo BL®) in...