GVT7C1325A Datasheet | Cypress

( Data Sheet : .. ) 325A CY7C1325A/GVT71256E18 256K x 18 Synchronous Flow-Through Burst SRAM Features - - - - - - - - - - - - - - - - Fast access times: 7.5 and 8 ns Fast clock speed: 117 and 100 MHz Provide high-performance 2-1-1-1 access rate Fast OE access times: 4.0 ns 3.3V - 5% and +10% power supply 2.5V or 3.3V I/O supply 5V tolerant inputs except I/Os Clamp diodes to VSSQ at all inputs and outputs mon data inputs and data outputs Byte Write Enable and Global Write control Three chip enables for depth expansion and address pipeline Address, data and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid Array) and 100-pin TQFP packages The CY7C1325A/GVT71256E18 SRAM integrates 262,144x18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (WEL, WEH, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and Burst Mode Control (MODE), and Sleep Mode Control (ZZ). The data outputs (DQ), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. WEL...