GVT7C1359A Datasheet | Cypress

( Data Sheet : .. ) CY7C1359A/GVT71256T18 256K x 18 Synchronous-Pipelined Cache Tag RAM Features - - - - - - - - - - - - - - - - - - - Fast match times: 3.5, 3.8, 4.0 and 4.5 ns Fast clock speed: 166, 150, 133, and 100 MHz Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns Pipelined data parator Data input register load control by DEN Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V - 5% and +10% core power supply 2.5V or 3.3V I/O supply 5V tolerant inputs except I/Os Clamp diodes to VSS at all inputs and outputs mon data inputs and data outputs JTAG boundary scan Byte Write Enable and Global Write control Three chip enables for depth expansion and address pipeline Address, data, and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications Low-profile JEDEC standard 100-pin TQFP package All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables (WEL, WEH, and BWE), Global Write (GW), and Data Input Enable (DEN). Asynchronous inputs include the Burst Mode Control (MODE), the Output Enable (OE) and the Match Output Enable (MOE). The data outputs (Q) and Match Output (MATCH), enabled by OE and MOE respectively, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV). Data inputs are registered with Data Input Enable (DEN) and chip enable pins (CE, CE2, and CE2). The outputs of the data input registers are pared with data in the memory array and a match signal is...