MB9B500B Datasheet | Cypress

MB9B500B Series 32-bit Arm® Cortex®-M3 FM3 Microcontroller The MB9B500B Series are a highly integrated 32-bit microcontroller that target for high-performance and cost-sensitive embedded control applications. The MB9B500B Series are based on the Arm® Cortex®-M3 Processor and on-chip Flash memory and SRAM, and peripheral functions, including Motor Control Timers, ADCs and munication Interfaces (USB, CAN, UART, CSIO, I2C, LIN). The products which are described in this data sheet are placed into TYPE0 product categories in "FM3 Family Peripheral Manual". Features 32-bit Arm® Cortex®-M3 Core - Processor version: r2p0 - Up to 80 MHz Frequency Operation - Memory Protection Unit (MPU): improve the reliability of an embedded system - Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels - 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] - Up to 512 Kbyte - Read cycle: 0wait-cycle@up to 60 MHz, 2wait-cycle- above - : Instruction pre-fetch buffer is included. So when CPU access continuously, it bees 0wait-cycle - Security function for code protection [SRAM] This series contain a total of up to 64 Kbyte on-chip SRAM. This is posed of two independent SRAM(SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. - SRAM0: Up to 32 Kbyte - SRAM1: Up to 32 Kbyte USB Interface USB interface is posed of Device and Host. PLL for USB is built-in, USB clock can be generated by multiplication of Main clock. [USB Device] - USB2.0 Full-Speed supported - Max. 6 End Point supported  End Point 0 is control transfer  End Point 1-5 can be selected bulk-transfer or interrupt- transfer - End Point 1-5 is prised Double Buffer [USB Host] - USB2.0 Full/Low speed supported - Bulk-transfer and interrupt-transfer and Isochronous- transfer...