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PSoC4500S - Programmable System-on-Chip

General Description

PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm® Cortex®-M0+ CPU.

It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.

Key Features

  • 32-bit MCU Subsystem.
  • 48-MHz Arm Cortex-M0+ CPU with single-cycle multiply.
  • Up to 256 KB of flash with Read Accelerator.
  • Up to 32 KB of SRAM.
  • 8-channel DMA engine.
  • Two Divide and Square Root computation accelerators Programmable Analog.
  • Four opamps with reconfigurable high-drive external and high-bandwidth internal drive and Comparator modes and ADC input buffering capability. Opamps can operate in Deep Sleep low-power mode.
  • Two 12-bit 1-Msps SAR ADCs with di.

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Full PDF Text Transcription for PSoC4500S (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for PSoC4500S. For precise diagrams, and layout, please refer to the original PDF.

PSoC 4: PSoC 4500S Datasheet Programmable System-on-Chip (PSoC) General Description PSoC® 4 is a scalable and reconfigurable platform architecture for a family of program...

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lable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm® Cortex®-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. PSoC 4500S is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity.

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