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C5002 - Low Skew Multiple Frequency PCI Clock Generator

General Description

Pin Number 2 Pin Name XIN 3 XOUT 1 VDDA 5 12, 16, 20, 24, 28 6 7 27 26 23 22 19 18 15 14 11 10 4, 8, 9, 13, 17, 21, 25 1 28 24 20 16 12 OE VDD SDATA SCLK REFCLK0/S0 CLK1/S1 CLK2/S2 CLK3/S3 CLK4/S4 CLK5/S5 CLK6/S6 CLK7/S7 CLK8/S8 CLK9/S9 VSS VDD VDD1 VDD2 VDD3 VDD4 VDD5 PWR VDDA VDDA - VDDA VDD

Key Features

  • Produces PCI output clocks that are individually selectable for 33.3 or 66.6 MHz under SMBus or strapping control.
  • Separate output buffer power supply for reduced noise, crosstalk and jitter.
  • input clock frequency standard 14.31818 MHz.
  • Output clocks frequency individually selectable via SMBus or hardware bi-directional pin strapping.
  • SSCG EMI reduction at 1.0% width.
  • Individual clock disables via SMBus control.
  • All output clocks skewed within a 500 pS win.

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Full PDF Text Transcription (Reference)

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C5002 Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG Approved Product Product Features § Produces PCI output clocks that are individually selectable for 33.3 or 66.6 MHz under SMBus or strapping control. § Separate output buffer power supply for reduced noise, crosstalk and jitter. § input clock frequency standard 14.31818 MHz § Output clocks frequency individually selectable via SMBus or hardware bi-directional pin strapping. § SSCG EMI reduction at 1.