Description
The CY7C1460SV25/CY7C1462SV25 are 2.5 V, 1M × 36/2M × 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL logic, respectively.
They are designed to support unlimited true back to back Read/Write operations with no wait states.
Features
- Pin compatible and functionally equivalent to ZBT™.
- Supports 250-MHz bus operations with zero wait states.
- Available speed grades are 250 and 167 MHz.
- Internally self-timed output buffer control to eliminate the need
to use asynchronous OE.
- Fully registered (inputs and outputs) for pipelined operation.
- Byte Write capability.
- 2.5-V core power supply.
- 2.5-V I/O power supply.
- Fast clock-to-output times.
- 2.6 ns (for 250-MHz device).
- Clock Enabl.