CY7C1518AV18 - 72-Mbit DDR-II SRAM

Product Overview

Cypress

Part number	CY7C1518AV18
Manufacturer	Cypress
File Size	926.58 KB
Description	72-Mbit DDR-II SRAM
Datasheet	CY7C1518AV18 Datasheet
Additional preview pages of the CY7C1518AV18 datasheet.

The CY7C1518AV18 and CY7C1520AV18 are 1.8 V synchronous pipelined SRAM equipped with DDR-II architecture.

The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.

Configurations.
72-Mbit density (4 M × 18, 2 M × 36).
300-MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at 600 MHz) at 300 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) simplify data capture in high-speed systems.

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Published: Dec 2, 2025 |