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CY7C1518AV18 - 72-Mbit DDR-II SRAM

General Description

The CY7C1518AV18 and CY7C1520AV18 are 1.8 V synchronous pipelined SRAM equipped with DDR-II architecture.

The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.

Key Features

  • Configurations.
  • 72-Mbit density (4 M × 18, 2 M × 36).
  • 300-MHz clock for high bandwidth.
  • Two-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces (data transferred at 600 MHz) at 300 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo clocks (CQ and CQ) simplify data capture in high-speed systems.

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📁 Similar Datasheet

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1520AV18 72-Mbit DDR-II SRAM
CY7C1006D 1-Mbit (256K x 4) Static RAM
CY7C1011G 2-Mbit (128K words x 16 bit) Static RAM
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1518AV18 CY7C1520AV18 72-Mbit DDR-II SRAM Two-Word Burst Architecture 72-Mbit DDR-II SRAM Two-Word Burst Architecture Features Configurations ■ 72-Mbit density (4 M × 18, 2 M × 36) ■ 300-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 600 MHz) at 300 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Synchronous internally self-timed writes ■ DDR-II operates with 1.