Description
The CY7C1518AV18 and CY7C1520AV18 are 1.8 V synchronous pipelined SRAM equipped with DDR-II architecture.
The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.
Features
- Configurations.
- 72-Mbit density (4 M × 18, 2 M × 36).
- 300-MHz clock for high bandwidth.
- Two-word burst for reducing address bus frequency.
- Double data rate (DDR) interfaces
(data transferred at 600 MHz) at 300 MHz.
- Two input clocks (K and K) for precise DDR timing.
- SRAM uses rising edges only.
- Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches.
- Echo clocks (CQ and CQ) simplify data capture in high-speed
systems.
CY7C1520AV18 Datasheet
