CY7C1520AV18 Datasheet | Cypress

CY7C1518AV18 CY7C1520AV18 72-Mbit DDR-II SRAM Two-Word Burst Architecture 72-Mbit DDR-II SRAM Two-Word Burst Architecture Features Configurations - 72-Mbit density (4 M × 18, 2 M × 36) - 300-MHz clock for high bandwidth - Two-word burst for reducing address bus frequency - Double data rate (DDR) interfaces (data transferred at 600 MHz) at 300 MHz - Two input clocks (K and K) for precise DDR timing - SRAM uses rising edges only - Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches - Echo clocks (CQ and CQ) simplify data capture in high-speed systems - Synchronous internally self-timed writes - DDR-II operates with 1.5 cycle read latency when delay lock loop (DLL) is enabled - Operates as a DDR-I device with one cycle read latency in DLL off mode - 1.8-V core power supply with HSTL inputs and outputs - Variable drive HSTL output buffers - Expanded HSTL output voltage (1.4 V- VDD) - Available in 165-ball FBGA package (15 × 17 × 1.4 mm) - Offered in both Pb-free and non Pb-free packages - JTAG 1149.1 patible test access port - DLL for accurate data placement Selection Guide CY7C1518AV18 - 4 M × 18 CY7C1520AV18 - 2 M × 36 Functional Description The CY7C1518AV18 and CY7C1520AV18 are 1.8 V synchronous pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C and C are not provided. On CY7C1518AV18 and CY7C1520AV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1518AV18 and two 36-bit words in the case of CY7C1520AV18 sequentially into or out of the device. Asynchronous inputs include an output...