CY9BF522M Datasheet | Cypress

CY9B520M Series 32-bit Arm® Cortex®-M3 FM3 Microcontroller The CY9B520M Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and petitive cost. These series are based on the Arm® Cortex®-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, DACs and munication Interfaces (USB, CAN, UART, CSIO, I2C, LIN). The products which are described in this data sheet are placed into TYPE9 product categories in “FM3 Family Peripheral Manual”. Features 32-bit Arm® Cortex®-M3 Core - Processor version: r2p1 - Up to 72 MHz Frequency Operation - Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels - 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] - Dual operation Flash memory  Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously.  Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank)  Work area: 32 Kbytes (lower bank) - Read cycle: 0 wait-cycle - Security function for code protection [SRAM] This Series on-chip SRAM is posed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. - SRAM0: Up to 16 Kbytes - SRAM1: Up to 16 Kbytes USB Interface The USB interface is posed of Device and Host. PLL for USB is built-in, USB clock can be generated by multiplication of Main clock. [USB device] - USB2.0 Full-Speed supported - Max 6 End Point supported  End Point 0 is control transfer  End Point 1, 2 can select Bulk-transfer, Interrupt-transfer or Isochronous-transfer  End Point 3 to 5 can select Bulk-transfer or Interrupt-transfer  End Point 1 to 5 are prised of Double Buffers.  The size of each endpoint is...