S27KS0642 Datasheet | Cypress

S27KL0642/S27KS0642 3.0 V/1.8 V, 64 Mb (8 MB), Hyper RAM Self-Refresh DRAM S27KL0642/S27KS0642, 3.0 V/1.8 V, 64 Mb (8 MB), Hyper RAM Self-Refresh DRAM Features Interface - Hyper Bus Interface - 1.8 V / 3.0 V interface support - Single-ended clock (CK) - 11 bus signals - Optional differential clock (CK, CK#) - 12 bus signals - Chip Select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional Read-Write Data Strobe (RWDS) - Output at the start of all transactions to indicate refresh latency - Output during read transactions as Read Data Strobe - Input during write transactions as Write Data Mask - Optional DDR Center-Aligned Read Strobe (DCARS) - During read transactions RWDS is offset by a second clock, phase shifted from CK - The Phase Shifted Clock is used to move the RWDS transition edge within the read data eye Performance, Power, and Packages - 200 MHz maximum clock rate - DDR - transfers data on both edges of the clock - Data throughput up to 400 MBps (3,200 Mbps) - Configurable Burst Characteristics - Linear burst Performance Summary Read Transaction Timings Maximum Clock Rate at 1.8 V VCC/VCCQ Maximum Clock Rate at 3.0 V VCC/VCCQ Maximum Access Time (t...