Infineon Technologies S27KS0642
64Mb self-refresh DRAM
| Part No. | S27KS0642 |
|---|---|
| Datasheet | S27KS0642 Download |
| Manufacturer |  Infineon Technologies |
| Description | 64Mb self-refresh DRAM |
| Buy | Stock & Price |
FEATURES
● Interface - HYPERBUS™ interface - 1.8 V / 3.0 V interface support● Single-ended clock (CK) - 11 bus signals
● Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data strobe (RWDS)
● Output at the start of all transactions to indicate refresh latency
● Output during read transactions as Read data strobe
● Input during write transactions as Write data mask - Optional DDR center-aligned read strobe (DCARS)
● During read transactions RWDS is offset by a second clock, phase shifted from CK
● The phase shifted clock is used to move the RWDS transition edge within the read data eye
● Performance, power, and packages - 200 MHz maximum clock rate - DDR - transfers data on both edges of the clock - Data throughput up to 400 MBps (3,200 Mbps) - Configurable burst characteristics:
● Linear burst - Wrapped burst lengths:
● 16 bytes (8 clocks)
● 32 bytes (16 clocks)
● 64 bytes (32 cloc...
