Datasheet Summary
Not Remended for New Designs (NRND)
S27KL0641/S27KS0641 S70KL1281/S70KS1281
3.0 V/1.8 V, 64 Mb (8 MB)/128 Mb (16 MB), HyperRAM™ Self-Refresh DRAM
3.0 V/1.8 V, 64 Mb (8 MB)/128 Mb (16 MB), HyperRAM™ Self-Refresh DRAM
Distinctive Characteristics
HyperRAM™ Low Signal Count Interface
- 3.0 V I/O, 11 bus signals
- Single ended clock (CK)
- 1.8 V I/O, 12 bus signals
- Differential clock (CK, CK#)
- Chip Select (CS#)
- 8-bit data bus (DQ[7:0])
- Read-Write Data Strobe (RWDS)
- Bidirectional Data Strobe / Mask
- Output at the start of all transactions to indicate refresh latency
- Output during read transactions as Read Data Strobe
- Input during write transactions as Write Data Mask
- RWDS...