Datasheet Summary
S70KL1283, S70KS1283
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Features
- Interface
- xSPI (Octal) interface
- 1.8 V / 3.0 V interface support
- Single ended clock (CK)
- 11 bus signals
- Optional differential clock (CK, CK#)
- 12 bus signals
- Chip Select (CS#)
- 8-bit data bus (DQ[7:0])
- Hardware reset (RESET#)
- Bidirectional read-write data strobe (RWDS)
- Output at the start of all transactions to indicate refresh latency
- Output during read transactions as read data strobe
- Input during write transactions as write data mask
- Optional DDR center-aligned read strobe (DCARS)
- During read transactions RWDS is offset by a second clock, phase shifted from CK
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