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S70KS1283 - 128Mb self-refresh DRAM

Download the S70KS1283 datasheet PDF. This datasheet also covers the S70KL1283 variant, as both devices belong to the same 128mb self-refresh dram family and are provided as variant models within a single manufacturer datasheet.

General Description

1.1 xSPI (Octal) interface 6 2 Product overview 9 2.1 xSPI (Octal) interface 9 3 Signal description 10 3.1 Input/output summary10 4 xSPI (Octal) transaction details11 4.1 Command/addre

Key Features

  • Interface - xSPI (Octal) interface - 1.8 V / 3.0 V interface support.
  • Single ended clock (CK) - 11 bus signals.
  • Optional differential clock (CK, CK#) - 12 bus signals - Chip Select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data strobe (RWDS).
  • Output at the start of all transactions to indicate refresh latency.
  • Output during read transactions as read data strobe.
  • Input during write transactions as w.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (S70KL1283-Infineon.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
S70KL1283, S70KS1283 128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) Octal xSPI, 1.8 V/3.0 V Features • Interface - xSPI (Octal) interface - 1.8 V / 3.