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DTC34LF86L - +3.3V LVDS 24Bit Flat Panel Display (FPD) Receiver

Datasheet Summary

Description

The D TC34LF86L/LR86L rec eivers co nvert the L VDS (Low Voltage Differential Signaling) data streams back into 28 bit s of CMOS/ TTL dat a with falling edge (DTC34LF86L) or risin g edge (DTC34LR86L) clock for convenient int erface with a variet y of L CD p anel controllers.

Features

  • ▓ Wide frequency range : 20 to 85 MHz shift clock support Narrow bus (10 lines) reduces cable size ▓ Sing le 3.3V supply ▓ Po wer-Down Mode ▓ ▓ ▓ ▓ ▓ ▓ ▓ ▓ Single pixel per clock XGA (1024x768) ready Supports VGA, SVGA, XGA and SXGA Up to 297.5 Megabytes/sec bandwidth Up to 2.38 Gbps throughput 300mV swing LVDS devices for low EMI PLL requires no external components Low profile 56-lead TSSOP package (PB Free) Compatible with the National DS90C386, T hine THC63LVDF84A Falling/Rising edg e rec.

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Datasheet Details

Part number DTC34LF86L
Manufacturer DOESTEK
File Size 234.40 KB
Description +3.3V LVDS 24Bit Flat Panel Display (FPD) Receiver
Datasheet download datasheet DTC34LF86L Datasheet
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Full PDF Text Transcription

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DTC34LF8 6L/DTC34LR86L LVDS Product DTC34LF86L/DTC34LR86L (Rev. 2.2) +3.3V LVDS 24Bit Flat Panel Display (FPD) Receiver - 85MHz General Description The D TC34LF86L/LR86L rec eivers co nvert the L VDS (Low Voltage Differential Signaling) data streams back into 28 bit s of CMOS/ TTL dat a with falling edge (DTC34LF86L) or risin g edge (DTC34LR86L) clock for convenient int erface with a variet y of L CD p anel controllers. A phase-locked transmit clock is transmitte d in p arallel with the data streams ove r a fif th L VDS link. A a transmitter (DTC34LM85L) w ill inter-o perate w ith without any translation logic. Using a 8 5 MHz clock, the dat a throu ghputs is 297.5 Mbytes/sec.
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